High Speed PCB Stack-Up Design: Best Layer Configurations and Materials

Electronics today are used in frequencies where time variations on a nanosecond are fatal. An example is a 10 Gbps data link which is ubiquitous in modern systems and which allows propagation delays as short as 0.1 nanoseconds - the time required by light to travel about 1 centimeter. All of the micrometers of the conductor routing, all of the microfarads of the dielectric separation, each decision in laminate material is crucially important at these speeds: systems work or die disastrously.

High speed PCB design

https://www.fanypcb.com/product/details/34.html not only does not start with component placement or trace routing but starts with stack-up architecture. This vertical structure, which is the stack-up the alignment of signal layers, power planes and ground planes, forms the basis of electrical foundation on which signal integrity relies on. Even a routed design created with flawless tracks falls pit to a poorly thought stack-up. A well-designed stack-up facilitates the operation on a high speed but is within manufacturing margins and economies.

Optimal Layer Structures: Signal- Reference Signal Architecture

There is a very basic rule to high speed PCB design that each signal layer must have an adjacent reference plane (power or ground) in place to allow the signal a low-impedance return path. It is a 4 layer form of architecture commonly denoted as S-G-P-S, and has minimized the current loop area, which means it is less inductive, and also generates less radiated EMI.

When using 6-layer boards, the Signal-Ground-Power-Power-Ground-Signal is the best allowed setup. This symmetric arrangement gives the signal layers a direct reference plane, which is required in controlled impedance. The power is efficiently distributed by the center power planes which are sandwiched together and the voltage drops are minimized.

The plan will change in 8+ layer boards: the board will add ground planes (not signal) instead of signal planes. An example of such a 10-layer configuration is of format S-G-S-G-S-P-S-G-S-G, so that no signal layer is farther than one reference plane away. This rule/principle is known as reference-plane adjacency and all considerations regarding stack-up are overridden by this. Breaking this basic rule causes impedance discontinuities that distort signal quality irrespective of trace width calculations.

The significance of symmetry: Because of asymmetrical stack-ups, there is differential expansion in the thermal cycling. A board that has all the ground planes at one face and the signal layers at the other will bend and cause mechanical stress and failures to the reliability. Symmetry The arrangement of the layers is a mirror over the center of the board and ensures warping is prevented with manufacturing tolerances maintained throughout the life of the product.

Choosing Material: Trade-offs between Performance and Manufacturability

FR-4 is the industry standard, and it can provide good performance on applications with speeds under 5 GHz. Normal FR-4 has dielectric constant (Dk) values of 4.5-4.7 that is fairly stable through the frequencies. Where price is a factor, FR-4 will do.

Filter-thin laminates are needed in high-speed applications at more than 5 GHz frequency. PTFE (Teflon)-based materials provide dielectric constant of 2.2-2.6 and loss tangent (tan 2) of almost 0.002-10 times that of FR-4 of 0.015-0.025. This 10-15x decimation in loss directly corresponds to signal integrity being conserved at very high distances and frequencies. There comes a cost, however, with PTFE manufacture; it is not hard like FR-4, and drilling and etching are difficult with it. Cost multiplies 3-5x versus FR-4.

There is a compromise in ceramic-filled hydrocarbon materials with dielectric constant 3.0-3.5, loss tangent 0.003-0.004, and more manufacturability than PTFE. These materials are 2-3x higher than normal FR-4 and they provide a performance comparable to PTFE up to 10 GHz.

Critical reflection: Stability of dielectric constant. Dielectric constant is dependent on frequency - The Dk of FR-4 may vary by up to -10 percent over a 1-10 GHz band. This variation leads to distortion of impedance compromising signal timing. Low-loss laminates have a Dk variation of ±2-3% which is critically needed in designs with multi-gigahertz bandwidth with ±3% tolerance of impedances.

Controlled Impedance: The Moat Technical Problem

The calculation of impedance is based on four variables, which include trace width, dielectric thickness, dielectric constant and proximity to reference planes. Signal trace designs close to ground (microstrip) and trace between-ground plane designs (stripline) must be designed differently to attain the same impedance.

At 50 Impedance of normal FR-4 with 1.2 mil dielectric thickness:

● Microstrip: 6.5-7.5 mil trace width
● Stripline: 4.5-5.5 mil trace width

Dielectric tolerance of -10, trace width tolerance of -15 led to a variation in impedance of -10-15. The designers should aim at marginally-designed impedance (design with 50 0 -10 ratio, not 50 0). The partnership with manufacturing companies that have used pcb design services https://www.fanypcb.com/pcb/layout and providers of pcb fabrication services makes sure that the stack-up designs are based on actual manufacturing capabilities, and not an ideal.

Best Practices with Professional Design Services

Professional pcb design services utilize electromagnetic inspection simulation confirmation of stack-up impedance ahead of the design. Things such as HyperLynx and SIwave model signal propagation, which indicate reflections, crosstalk, and timing skew, which are missed by calculation only. This prior validation of pre-fabrication saves costly re-designing.

The most respected pcb fabrication service https://www.fanypcb.com/pcb/fabrication companies provide the IPC-2851 stack-up documentation, which is a standardized definition of the layers that gives the exact dielectric constant of the layers, laminate thickness, and the manufacturing process. Designers, who insist upon such specifications, as opposed to generic stacks which are labeled as standard, guarantee such impredance control by manufacture.

Summing up: Stack-Up Competitive Advantage

The success of high speed PCB design largely relies on the careful stack-up engineering -the organization of the layers, choice of material and impedance control to support contingent signal propagation at the gigahertz frequencies. Firms that invest in, and have expert stack-up design, their first-pass success, less EMI, better signal integrity, and low time-to-market. Individuals that fail to do this at the start of the design experience failed fields, costly redesigns, and competitive losses.

The stack-up is the backbone. Everything else is detail.

This release was published on openPR.